Author(s)

Jin Shi

Corresponding Author

Jin Shi

Abstract

Due to advantages in performance, cost, power consumption, etc., signal processing modules based on FPGA and DSP Builder have been widely used in various signal processing fields. At present, FPGAs and DSP Builders generally implement fixed-point number calculations for FIR filters. Due to the limited fixed-point number length, they cannot meet the accuracy requirements. Therefore, FPGAs are used to implement high-speed, high-precision floating-point high-order FIR filters. Very important significance. In this paper, the digital signal processing model is established graphically in MATLAB/SIMULINK environment to design and simulate the DSP BUILDER, and the designed graphic file .mdl is directly converted into a C language program to run in CCS. By adding AD and D/A interface programs, the software can be downloaded to the DSP BUILDER target board after debugging and compilation. This article introduces the advantages of FPGA in digital filter design and application. The inherent flexibility of FPGAs also allows designers to keep up with the changes in the new standards, and can provide feasible methods to meet the changing standards. This article discusses the basic principles of multi-rate signal processing, proposes an improvement of the multi-phase structure, and does some theoretical research on the application of FPGAs in multi-rate signal processing. Research shows that this paper builds a 70-tap linear phase FIR filter as an example, and only requires four 256 input and one 8 input LUT. You can use a simple adder tree to connect their outputs. It can be seen that the fully parallel structure has the best performance, but it also consumes the most resources.

Keywords

FPGA Distributed Algorithm; Digital Filter; FIR Multi-Rate Signal Processing; DSP Builder Processing Module