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The Implementation of Digital Down Converter System based on QuartusⅡ

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DOI: 10.38007/Proceedings.0000085

Author(s)

Jingjing Zhang and Chenming Li

Corresponding Author

Jingjing Zhang

Abstract

The main work of DDC is as follows: on the one hand, the wideband signals including all channels are separated to extract the required narrowband signals; on the other hand, for the separated narrowband signals, according to the sampling theorem, the amount of data can be reduced and the processing pressure of baseband part can be relieved. The performance of digital down conversion directly affects the performance of the whole digital demodulator. In this paper, when the input if frequency is variable, the AD sampling rate is changed to adapt to the IF frequency. That is, DDC and DDS are combined. This paper describes the implementation of DDC when the IF signal frequency is from 60MHz to 80MHz and the symbol rate is 1.338m/s. Finally, the performance of digital down converter is simulated by Simulink, and the performance of digital down converter is measured by test circuit under Quartus II.

Keywords

DDC; FPGA; Halfband digital filter; QuartusⅡ